The following relates to the electrical and electronic arts. It finds particular application in semiconductor light emitting device packaging, and will be described with particular reference thereto. The following will find more general application in semiconductor device packaging entailing operative electrical connection of small semiconductor chips or semiconductor chips having small electrode gaps.
Some high power light emitting diode (LED) packages advantageously employ a flip-chip mounting configuration in which the anode and cathode electrodes are disposed on the same side of the chip, and are bonded to mating electrical pads. To reduce resistive losses and promote electrical current spreading, LED chips designed for flip-chip bonding typically include closely spaced, and optionally interleaved, anode and cathode electrodes. For example, the electrodes may be interleaved using an interdigitated finger arrangement, spiral intersections, or so forth. A consequence of this arrangement is that the gap between the mating electrical pads to which the chip is flip-chip bonded should be small. In some configurations, the gap between the mating electrical pads should be about 100 microns or less, and in some more rigorous configurations the gap should be about 80 microns or less.
This presents a problem, because conventional circuit boards have gaps between traces of order 150 microns or larger. Moreover, the minimum gap between traces increases with increasing thickness of the conductive layer. For high power LED packages, it is desirable to have a circuit board with a relatively thick conductive layer so as to promote heat sinking of the high power LED chip into the circuit board through the flip chip bonding connection.
It is known in the art to use a submount to accommodate the small electrode spacing of the LED chip to the wider-spaced electrical pads of the circuit board. Typically, a submount of silicon or other thermally conductive material is interposed between the LED chip and the circuit board. The submount has finely spaced electrical pads to which the LED chip is flip-chip bonded, and the submount in turn is electrically and mechanically attached to the circuit board in a suitable fashion that entails larger tolerances comporting with the wider spacing of the circuit board traces.
Submounts have certain disadvantages, however, including for example increased packaging complexity and concomitant yield reduction, introduction of additional thermal resistance due to the intervening submount, and possible incompatibilities between the submount material and processing operations performed after chip attachment to the submount.
Shelton et al., U.S. Publ. Appl. No. 2005/0194605 A1 published Sep. 8, 2005 discloses another approach for addressing this problem, in which one or more fanning layers are formed on the front-side of the LED chip. Each fanning layer includes a dielectric layer and one or more metal layers, and the topmost fanning layer defines electrical contact pads spaced apart widely enough to enable direct flip-chip bonding of the chip including the fanning layers to the circuit board. This approach is not readily applied to packaging of commercially available diced LED chips that do not include the aforementioned fanning layer or fanning layers.